| 摘要 |
PURPOSE:To realize word code conversion without using any ROM by providing an input register, code converting circuit, and output register, and alternating input timing and output timing. CONSTITUTION:NRZ Data Din is inputted to a shift register and a circuit 35 performs the acquisition of synchronism. The output Q of an FF24 synchronizes with a clock 1.5F.CLK to function as a load shift enable signal LSE. This signal when going down to a logical level 0 opens a load shift switching gate (NOR gate) 27. An AND gate 29 discriminates the mode of the NRZ data and its output S is impressed to a presetting circuit 37. The counted value of a counting circuit 36 indicates the extent of the bit shifting of the shift register 28. The NRZ data is code-converted asynchronously with the clock and loaded into a register 28 in parallel. This conversion is performed by a code converting logical circuit 38. The circuit 36 sends out a load shift switching output LS', which is passed through the switching gate 27 to obtain a load shift switching output LS, alternating loading and shifting successively. |
