发明名称 ARITHMETIC PROCESSING UNIT
摘要 PURPOSE:To obtain the absolute value of two data or the complementary number of two data at high speed by obtaining the result of first and second data in an addition inversion means, simultaneously obtaining the result of second and first data in an addition means, and selecting the output of both means through the use of an overflow value. CONSTITUTION:An arithmetic processor consists of an inverter 101, an addition inverter 102, an adder 103, and a selection circuit 104. Namely, the inverse of X of all digits in first input data are obtained in the inverter 101, and it is inputted to the addition inverter 102 with second input data Y. The inverse of first data X and data Y are added and all the digits of the result are inversed, whereby X-Y is obtained. At the same time, the inverse of first data X and data Y are inputted to the adder 103, and -X+Y+1 in which '1' is added from the lowest-order is outputted as the inverse of X, data Y and a carry signal, whereby X-Y is decided to be positive or negative by using a high-order overflow signal 105. When it is positive, the output of the inverter 102 is selected in the circuit 104, and the output of the adder 103 when it is negative, whereby it is outputted as the absolute value X-Y.
申请公布号 JPH01205328(A) 申请公布日期 1989.08.17
申请号 JP19880031239 申请日期 1988.02.12
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 TANIGUCHI TAKASHI
分类号 G06F7/50;G06F7/506;G06F7/508;G06F7/544 主分类号 G06F7/50
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