发明名称 Circuit arrangement for reducing noise
摘要 A circuit arrangement for reducing noise when peaking the edges of a useful signal (S1) by combination with a peaking signal (S3) derived therefrom, which signal only influences the useful signal (S1) when a predetermined amplitude threshold is exceeded, which arrangement has a peaking signal stage (20) for supplying the peaking signal (S3) and a noise suppression stage (7) in which a noise suppression signal is generated and is superimposed on the peaking signal (S3), while the peaking signal stage (20) applies the peaking signal (S3) to two push-pull current outputs (21, 22) provides the possibility of a very simple circuit structure, particularly with a view to a space-saving integration on a semiconductor crystal in that each of the push-pull current outputs (21, 22) in the noise suppression stage (7) is connected to a series resistor (23, 24) and to the control terminal of one of two transistors (25, 26) whose main current paths at one end are connected together and to a supply current source (27) and at their other end are connected to the terminal of the associated series resistor (23, 24) remote from the push-pull current output (21, 22, respectively).
申请公布号 US4857779(A) 申请公布日期 1989.08.15
申请号 US19880208195 申请日期 1988.06.16
申请人 U.S. PHILIPS CORPORATION 发明人 HARLOS, HARTMUT;KELTING, PETER
分类号 H04N5/208;H03G7/00;H03K5/12;H03K5/1252;H04N5/21 主分类号 H04N5/208
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