| 摘要 |
PURPOSE:To attain retiming of an input data by using a digital signal to initialize the internal state, retarding an output signal applying 1/2 frequency division to a clock signal by a half clock of the clock signal. CONSTITUTION:Clock signals represented by output signals c, c' of an inverter circuit 106 have a different phase from clock signals b, b' of a frequency 2f0 inputted from a clock input line 102 by T/4. Clock signals c,c' are used to segment output signals d, d' of a 1/2 frequency division circuit 104 by a D-F/F 105. That is, clock signals e, e' are signals with a retarded phase by T/4 in comparison with the output signals d, d'. The rising of the clock signals e, e' appears at a phase point retarded by T/4-3T/4 from the change point of the input data signal (a). Thus, the clock signals e, e' are used to apply retiming to the input data signal (a) without error. |
