| 摘要 |
<p>Technology for preventing parasitic capacitance of a MIS-type capacitor. A semiconductor device comprises an n-type semiconductor region (32) formed on a p-type semiconductor substrate (31), and a p-type semiconductor region (34) formed therein. A first electrode (38a) that forms a capacitor is provided on the p-type semiconductor region (34) via a dielectric layer (37), a third electrode (38c) is provided that is connected to the p-type semiconductor region (34), and a second electrode (38b) is provided that is connected to the n-type semiconductor region (32). The first or the third electrode is connected to input terminals of a buffer circuit, and the second electrode is connected to an output terminal of the buffer circuit. Therefore, the capacitance (capacitor) is not affected by the junction capacitance between the semiconductor layers of different conduction types.</p> |
