发明名称 INITIAL PHASE MATCHING CIRCUIT FOR PHASE LOCKED LOOP OSCILLATOR
摘要 PURPOSE:To reduce the pull-in time of a phase locked loop oscillator by dividing a clock of a voltage controlled oscillator circuit giving to a phase comparator circuit in polyphase and selecting a phase of a clock of the voltage controlled oscillation circuit having a phase closest to the phase of a readout data from a disk medium. CONSTITUTION:A phase comparator circuit 4 and a voltage controlled oscillation circuit 6 used for a disk device are both operated, an output clock of the voltage controlled oscillator circuit 6 given to the phase comparator circuit 4 is divided into polyphase and one clock is selected from the polyphase clocks according to the condition and used. That is, the clock of the voltage controlled oscillation circuit 6 is divided into three phases, and one clock with the least phase difference from the phase of the data read from a disk medium is selected from the three phase clocks of the voltage controlled oscillation circuit 6. Thus, the phase locked oscillator with small pull-in time is obtained.
申请公布号 JPH01181323(A) 申请公布日期 1989.07.19
申请号 JP19880006665 申请日期 1988.01.14
申请人 NEC CORP 发明人 OKADA YOSHIAKI
分类号 H03L7/08;G11B20/14 主分类号 H03L7/08
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