发明名称 DIGITAL PLL CIRCUIT
摘要 PURPOSE:To quicken the pull in time and to suppress the period fluctuation of an output signal by using a mask signal to apply phase locking and providing a blind sector to a phase comparator. CONSTITUTION:An input signal and a mask signal are given to a mask decision circuit 4, the circuit 4 decides the relation of phase of both the input signals, and when the input signal is within the mask signal, an input signal in the mask is outputted and when the input signal is at the outside of the mask signal, the input signal at the outside of the mask is sent. The input signal within the mask is given to a phase comparator 1 and the input signal at the outside of mask is given to a variable period counter 2. A frequency division counter of a counter 2 is reset forcibly and starts counting in the same phase as that of the input signal. Thus, the input signal and the output signal reach the same phase at the next period and the phase locking is finished. On the other hand, the comparator 1 compares the phase of the input signal within mask with the phase of the output signal, and when the phase difference exceeds a prescribed value, a lead or lag signal is outputted. When the phase difference is within the dead band, the output signal is fixed to the reference period.
申请公布号 JPH01180118(A) 申请公布日期 1989.07.18
申请号 JP19880004075 申请日期 1988.01.12
申请人 MITSUBISHI ELECTRIC CORP 发明人 AKITA MASASHI
分类号 H03L7/06;H04L7/02;H04L7/033 主分类号 H03L7/06
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