发明名称 |
System for feeding clock signals |
摘要 |
A system for feeding clock signals to a plurality of load units comprises an oscillator for generating a first clock signal having a predetermined frequency, a plurality of signal lines for transmitting a signal representative of the first clock signal to a plurality of load units, and delays assigned to the plurality of signal lines for adjusting phases of the signal transmitted on a corresponding line at connection points between the oscillator and the load unit. Each load unit is responsive to the signal transmitted on a corresponding signal line for producing second clock signals with a frequency n times greater than that of the second clock signals where n is an integer greater than one. Each load unit further is responsive to the second clock signal for generating a plurality of third clock signals which have discrete phases. The plurality of load units are synchronized with at least one of the plurality of third clock signals.
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申请公布号 |
US4847516(A) |
申请公布日期 |
1989.07.11 |
申请号 |
US19870123939 |
申请日期 |
1987.11.23 |
申请人 |
HITACHI, LTD. |
发明人 |
FUJITA, BUNICHI;KAWASHIMA, SEIICHI |
分类号 |
H03L7/00;G06F1/10;H03K5/15;H03L7/23 |
主分类号 |
H03L7/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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