发明名称 ROUNDING PROCESSING SYSTEM IN BINARY FLOATING POINT MULTIPLICATION
摘要 PURPOSE:To decrease the number of processing steps and to execute the high speed of a processing by early detecting the generation of a mantissa overflow in a rounding processing and executing the rounding processing of the mantissa before regularizing processing. CONSTITUTION:The rounding processing when a mantissa overflow OVF 1 occurs and the rounding processing when it does not occur are prepared beforehand, and switching is executed to either of them by the presence and absence of the mantissa overflow OVF 1 generation. Namely, the rounding processing is executed by a rounding processing determining circuit 13 and a rounding adder 14 beforehand for the intermediate result before the regularizing processing, and a mantissa post-operation regularizing circuit 15 executes the regularizing processing including a mantissa overflow OVF 2 to occur by the rounding processing. Thus, the number of the processing steps is decreased and the high speed of the processing is executed.
申请公布号 JPH01171023(A) 申请公布日期 1989.07.06
申请号 JP19870328409 申请日期 1987.12.26
申请人 FUJITSU LTD 发明人 YOSHIDA YUJI
分类号 G06F7/38;G06F7/487;G06F7/508;G06F7/52 主分类号 G06F7/38
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