Accelerated validity response permitting early issue of instructions dependent upon outcome of floating point operations

摘要

Apparatus and method for accelerating a validity response provided by a floating point unit assures the validity of the present state of a condition code and an interrupt signal before the completion of a floating point arithmetic instruction whose result affects the condition code and interrupt signal. The accelerated validity response is derived from an evaluation of the exponents, signs, and fractions contained in the operands of a currently-executing floating point arithmetic operation which is made prior to or during execution of the instruction. Also provided is the capability of setting the condition code prior to the completion of certain add class floating point instructions where one of those instructions stimulates an early validity response. An accelerated interrupt request is also provided in synchronism with an accelerated validity response for certain floating point add and subtract instructions.