| 摘要 |
<p>A semiconductor device comprising a collector region (53) (a quantum well layer having high transverse conductance) located between gate region (55) and emitter region (50,51), a barrier layer (52) formed between emitter and collector regions, and a relatively thin barrier layer (54) formed between collector and gate regions. The chemical compositions and/or thickness of the various layers are chosen such that application of a voltage to the gate induces a two-dimensional charge carrier gas in the collector region (53) through which the gate field penetrates into the emitter barrier region (52) whereby a current between emitter and collector regions can be controlled by means of a voltage applied to the gate, and such that there is no substantial gate leakage due to tunneling through the gate barrier layer (54). Exemplarily the invention is embodied in a GaAs/AlGaAs heterostructure. It may further be possible to use an insulated gate technology. Such a three-terminal structure is expected to have a very high operating speed.</p> |
