发明名称 TIME CORRECTION PROCESSING METHOD FOR MULTIPLEXING SYSTEM
摘要 <p>PURPOSE:To obtain the resistance to trouble of the whole of a system against clock trouble by using one of internal clocks of plural processors as the representative clock and dynamically changing the time of this clock. CONSTITUTION:A time correction interrupting part 4 of a processor CPU 0 having a representative clock 3' writes the time of the representative clock 3' in a time area 21 at intervals of a prescribed time and interrupts another processor CPU 1 for the purpose of correcting the time. A time setting part 5 of the processor CPU 1 receives a time correction interrupt signal through a time correction interrupt storage part 22 in a shared memory M0. That is, an interrupt for time correction is generated. The time setting part 5 of the processor CPU 1 sets the time in the time area 21 to an internal clock T1 of the processor CPU 1, to which this part 5 belongs to, in accordance with this interrupt. Thus, the time of the internal clock T1 is matched to the time of the representative clock 3' at intervals of the prescribed time to correct the time of the internal clock T1.</p>
申请公布号 JPH02205910(A) 申请公布日期 1990.08.15
申请号 JP19890025220 申请日期 1989.02.03
申请人 PFU LTD 发明人 SHIMADA KAZUHIRO
分类号 G06F11/16;G06F1/14 主分类号 G06F11/16
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