Fabrication of FET integrated circuits.

摘要

A gate (7) is formed which has an insulating top (9) and sidewall spacers (17). A conductive window pad layer (23) is deposited so as to make contact with the source and drain regions (15,19,21). The window pad layer may overlap the gate (7) and/or field oxide (3). An insulating layer (25) is then laid down and windows are formed above the source and drain regions exposing portions of the window pad layer. Contacts (27) are made to the window pad layer through the windows. The window pad layer may be used to form conductive runners joining one source/drain region with another, in which case not every source/drain region needs a separate contact (27).