| 摘要 |
PURPOSE:To reduce the discrepancy between the delay times of respective clock signal wirings and avoid the variation of the delay times of the clock signals by a method wherein the application length ratio of a high resistivity wiring whose unit length resistance is high and a low resistivity wiring whose unit length resistance is low is adjusted in accordance with the length of the clock signal wiring. CONSTITUTION:For a flip-flop 4 whose wiring length is long, the ratio of a low resistivity clock wiring 7 in the wiring is large and the length of the high resistivity clock wiring 6 is short. For flip-flop 5 whose wiring length is short, the ratio of a high resistivity clock wiring 9 in the wiring is large and the length of the low resistivity clock wiring 8 is short. By adjusting the wiring resistance like this, the variation of the delay times of the clock signals can be avoided. As the more low resistivity clock wiring is employed when the clock wiring is long and the more high resistivity clock wiring is employed when the wiring length is short, the variation of the delay time can be reduced easily and the operation of the flip-flop can be stabilized. |
