| 摘要 |
PURPOSE:To obtain the logic of three parties and to improve the detecting accuracy of a synchronizing signal by adding to the first synchronizing signal detected by a coincident comparison with a synchronizing pattern and confirming a frame address value with an error detecting code system as one type of a synchronizing signal. CONSTITUTION:Serial type digital data from an input terminal 1 are inputted to shift register circuits 2-a-2-d, the output of the circuit 2-d is compared with the output from a synchronizing pattern generating circuit 4 with a synchronizing pattern comparing circuit 3 and a first synchronizing signal is detected. The data are inputted to a parity generating circuit 5 of circuits 2-c and 2-b, a prescribed operation with an ID code and a BA code is executed and added to a parity inspecting circuit 6. With the circuit 6, the parity inspection with the output from the circuit 2-a is executed and the inspection result is inputted to an AND circuit 7. The pseudo synchronizing signal outputted by the circuit 3 is removed, the output of the circuit 2-c, and a field pulse signal from the circuit 7 and an input terminal 8 are processed by a field address coincidence circuit and a synchronizing signal is detected with a high accuracy. |
