| 摘要 |
PURPOSE:To simplify circuits by providing a voltage controlled oscillator comprising a delay element and an inverter and a detection window pulse generating means comprising the delay element and an exclusive OR circuit. CONSTITUTION:As a generating means of a detection window pulse, a means comprising a delay element VDL1 consisting of multi-stage cascade connection circuit of CMOS inverters whose delay time is varied by a power voltage and comprising an exclusive OR circuit EXOR is used. As a voltage-controlled oscillator VCO, a means comprising a delay element VDL2 consisting of multi- stage cascade connection circuit of CMOS inverters whose delay time is varied by a power voltage and comprising an inverter INV is used. Thus, a bit clock signal whose duty cycle is 50% having a prescribed frequency is generated easily by only changing the power voltage of the multi-stage cascade connection circuit of CMOS inverters. |
