| 摘要 |
<p>PURPOSE:To attain the synchronism of a parity block without attaining a frame syn chronization, and at the same time, to realize the detection of a code error through simple constitution by constituting this method of a 1/2 frequency dividing means, a delaying means, a clock generating means, a coincidence detecting means and a deciding means. CONSTITUTION:The 1/2 frequency divider 7 outputs the value of an initial state or the inverted value of the initial state respectively when even numbers of '1' or odd numbers of '1' exist in an input data that the data of a parity block of mB1P codes, that the data of m-bits is added with the parity bit of one bit, is RZ-converted. The output of the frequency divider 7 is branched, and the output of one side is inputted to the m+1 bits delay circuit 9, and is delayed by prescribed number of bits. The coincidence detection circuit 10 inputs the other side of the branched output of the frequency divider 7 and the output of the delay circuit 9, and detects the coincidence of the input data of both, as shifting the timing of the clock of the output of the 1/(m+1) clock generation circuit 8. When the decision circuit 11 decides that the synchronization of the parity block is attained on account of the detection of the coincidence in the coincidence detection circuit 10, it fixes the timing of 1/m+1 clock, generated in the clock generation circuit 8, by its control signal.</p> |
