发明名称 |
VERTICAL MOSFET |
摘要 |
PURPOSE:To reduce a capacitance value between a gate and a drain by a method wherein a third semiconductor region which is of a first conductivity type and whose resistivity is lower than that of a second semiconductor layer is formed near the surface inside the second semiconductor layer. CONSTITUTION:An N-type semiconductor region 10 is formed near the surface of an N-type epitaxial layer 2 after one part of a gate electrode 4 in a region where the gate electrode 4 is superposed via a gate insulating film 3 on the surface of the N-type epitaxial layer 2 has been removed and while the removed gate electrode is used as a mask. Accordingly, a current path in an ON state is secured by the N-type semiconductor region 10 which has been formed on the surface of the N-type epitaxial layer 2; a width W2 to be removed of the gate electrode 4 can be made wider than a width to be removed of a conventional vertical-type MOSFET. By this setup, a capacitance value between a gate and a drain can be reduced sharply; a switching duration can be shortened and switching loss can be reduced. |
申请公布号 |
JPH01111378(A) |
申请公布日期 |
1989.04.28 |
申请号 |
JP19870269844 |
申请日期 |
1987.10.26 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
SAKAI TATSURO;YAMASHITA NOBUHIKO;MURAKAMI NAOKI |
分类号 |
H01L29/08;H01L29/423;H01L29/78 |
主分类号 |
H01L29/08 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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