| 摘要 |
Circuitry for aligning the transition of a clock signal to transitions of a horizontal line synchronizing signal includes a series of delay elements which provide a plurality of clock signal phases. The longest phase delay provided by this circuitry is greater than the period of the clock signal. The clock signal and the delayed clock signal phases are applied to circuitry which selects one clock signal phase, which has a transition occurring within a predetermined time interval of the transition in the horizontal line synchronizing signal. Other circuitry, coupled to this selection circuitry, inhibits the selection of any clock phase having a greater time delay than the selected phase. This prevents the selection of multiple clock phase signals.
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