| 摘要 |
PURPOSE: To escape the latch-up problem of a CMOS by interfacing between a first circuit having a prescribed supply voltage and a second circuit having a larger supply voltage than that supply voltage. CONSTITUTION: When a voltage beyond, for example, a 3.3 volt voltage impressed to the gate electrode of a pull-up transistor 30 only by a P channel 0.7 volt threshold voltage is impressed to a data output terminal 24, a transistor 30 is turned on, the voltage of the terminal 24 is supplied to a node B, a 0 volt is impressed to the gate electrode, and a control transistor 36 is turned on. Therefore, a high voltage on the data output terminal 24 is also supplied to a node C, and a switching transistor 32 is turned off so that currents can be prevented from being leaked to a first voltage source 28 and VDD. Thus, the latch-up problem of a CMOS can be prevented. |
