发明名称 LEVEL CONVERSION CIRCUIT
摘要 <p>PURPOSE:To adjust optionally the hysteresis width by interposing a voltage change means whose terminal voltage changes in response to the on/off of a current between an output terminal of the 2nd switching means and an output terminal of the 2nd constant current circuit. CONSTITUTION:Since the voltage drop of the voltage change means R10 is zero when the 2nd switching means Q8, Q9 are turned off, the input level (V2) when it is switched in the on-state is identical to the state when the voltage change means R10 does not exist. When the 2nd switching means Q8, Q9 are turned on, the current flowing to the 2nd constant current circuits Q4-Q6 flows to the voltage change means R10, a voltage drop in response to the current is caused. Thus, when the 2nd switching means Q8, Q9 are switched from ON to OFF, a control output terminal voltage is compared with a voltage being the sum of the voltage drop of the means R10 to the output terminal voltage of the constant current circuits Q4-Q6. Thus, the 2nd switching means Q8, Q9 are turned off, it is implemented at a voltage VA3 higher than the voltage VA2 when the means is switched to the ON-state. Thus, the hysteresis width (V2-V1) is decreased.</p>
申请公布号 JPS6467026(A) 申请公布日期 1989.03.13
申请号 JP19870223713 申请日期 1987.09.07
申请人 AISIN SEIKI CO LTD 发明人 HATAKEYAMA AKIRA;KIMURA NOBUYASU
分类号 H03K3/2893;H03K5/02;H03K19/00;H03K19/0175 主分类号 H03K3/2893
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