发明名称 |
Decoding circuit arrangement for redundant semiconductor storage systems |
摘要 |
A decoding process and a decoding circuit arrangement for a redundant semiconductor memory is described, wherein the advantages of parallelly selecting non-defective word lines and redundant word lines at a low level are utilized for the writing as well as for the reading current in such a manner that high speed reading and writing is not affected. This is achieved in that the decoder for the redundant word lines consists of a comparator circuit and fuse-controlled switches, and that the input addresses are applied to a conventional address decoder as well as to the comparator circuit. The output of the comparator circuit is directly connected to the input of a first driver circuit for the redundant word line, and furthermore to an OR circuit which is also controlled by a read/write control circuit, and which is connected to the decoder and to a clamp circuit that is directly connected to the input of a second word line driver circuit, and continuously maintains the potential following a deselect signal applied on that level, which requires a minimum of power.
|
申请公布号 |
US4811298(A) |
申请公布日期 |
1989.03.07 |
申请号 |
US19870087489 |
申请日期 |
1987.08.20 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
HELWIG, KLAUS;LOHLEIN, WOLFDIETER;TONG, MINH H. |
分类号 |
G11C11/408;G11C11/401;G11C29/00;G11C29/04;(IPC1-7):G11C13/00 |
主分类号 |
G11C11/408 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|