| 摘要 |
A sample-and-hold phase detector (30, 80, 90, 100, 110) which includes sample-and-hold circuitry (FIG. 6) having variable efficiency. Specifically, the sample-and-hold circuitry provides a sampling pulse of variable width which is controlled to be wider during acquisition and narrower during steady-state operation. Also provided is protection circuitry to neutralize leakage of the input signal to the output of the circuit when a sample control signal is not present.
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