| 摘要 |
A data processing system including a central processing unit which connects to two or more buses. The buses include a memory bus connected to a main store, and to two or more I/O devices sharing common control for accesses to the main store. Priority of transfers over the memory bus is determined by priority circuit in a two-way priority between the processing unit and the common I/O devices on the memory bus. One common I/O devices is a display unit and the other common I/O device is a direct memory access disk unit. The display is periodically refreshed. Priority is always granted to the display device. Priority is granted to the disk device as a supplement to a access by the display device. The direct memory access device piggybacks on the priority of the display device.
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