| 摘要 |
PURPOSE:To allow a processing with low priority to properly interrupt a processing with high priority by controlling various processing generated in a computer and executed in the order of priority so that the priority can be changed. CONSTITUTION:At first, '0' is loaded to a counter circuit 1 by operating software and then the start of counting operation is instructed. Consequently, the counter circuit 1 goes to a 4-bit counter for continuously counting up '0'-'F'. Since the 2<3>-th bit output is false during the period of count values '0'-'7', AND circuits 3a, 3b are disabled and AND circuits 3b, ad are formed, and when processing request signals A, B are simultaneously inputted, a processing request signal B appears as an output. When the counted values are '8'-'F', input signal A appears. When any one of the counted values '0'-'7' is loaded under said condition, the processing of the input signal A can be executed always with priority as compared to the input signal B. In the counted values '8'-'F', the input signal B is executed with priority. |
