发明名称 SYNCHRONISING APPARATUS FOR A DIGITAL SIGNAL DEMULTIPLEXER
摘要 The object consists of equalising a bit slip during the demultiplexing of a multiplex signal. A bit-slip detection device (10) detects a bit slip and controls a clock frequency switching circuit (11) in such a manner that the number of the bits output to the outputs (4a-4d) of the demultiplexer (3) is returned to the nominal value by accelerating or decelerating the clock at the main frame counter (8). The invention is used in digital signal demultiplexers. <IMAGE>
申请公布号 AU2019388(A) 申请公布日期 1989.02.02
申请号 AU19880020193 申请日期 1988.07.29
申请人 SIEMENS AKTIENGESELLSCHAFT 发明人 JOHANN MAGERL;WILHELM VOLEJNIK
分类号 H04J3/06 主分类号 H04J3/06
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