发明名称 INITIAL SET CIRCUIT
摘要 PURPOSE:To reduce the non-initial set time and to attain sure initial setting, by applying an output of an oscillating circuit to a mode set terminal of an integrated circuit by a prescribed time only via a time and level set circuit from the power-on of the integrated circuit. CONSTITUTION:The time/level set circuit comprising an oscillating circuit 41, a tri-state buffer circuit 42, a time constant circuit 43, and a pull-up resistor 44 is provided between an IC power supply Vcc and a mode set terminal 40 of an IC circuit 10. When the power supply Vcc is applied, the circuits 41, 43 are started and after a pulse signal is applied to the terminal 40 for a prescribed time, the terminal 40 is fixed to a level of logical 1 with the resistor 44. The waveform of an input signal to the terminal 40 is shaped at a Schmitt trigger buffer 32, and its output is applied to an in-phase delay circuit 33 delaying it for a prescribed time, an exclusive OR circuit 34 and a mode switching circuit. A power-on reset pulse is generated from the circuit 34 at each pulse and the IC10 is set initially with the pulse.
申请公布号 JPS5951624(A) 申请公布日期 1984.03.26
申请号 JP19820162646 申请日期 1982.09.18
申请人 FUJITSU TEN KK 发明人 OGAWA HIROSHI
分类号 H03K17/22 主分类号 H03K17/22
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