发明名称 FORMATION OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To cut down the time required for a lithographic process by a method wherein fine patterns of four adjacent semiconductor integrated circuits are gathered around the central part to be simultaneously formed into a block by means of a contraction projection exposure device. CONSTITUTION:A reticle 22 holding patterns to be transferred corresponding to fine patterns of overall contracted fine pattern formation parts 11b is prepared. Then, the patterns to be transferred held on the reticle 22 are successively transferred to the resist on a wafer by step and repeat shifting process using a contracted projection exposure device. At this time, a full-size exposure mask holding the patterns excluding the fine pattern formation parts 11b i.e. the patterns to be transferred corresponding to all rough patterns A on the wafer is prepared. The patterns to be transferred held on the mask by the full-size exposure device are temporarily transferred to the resist on the wafer. Through these procedures, the time required for lithographic process can be cut down.
申请公布号 JPS6428818(A) 申请公布日期 1989.01.31
申请号 JP19870183295 申请日期 1987.07.24
申请人 HITACHI LTD 发明人 NAKAGAWA SHINYA;KOMORIYA SUSUMU;MORITA MITSUHIRO;IRIKITA NOBUYUKI;INOUE MORIO
分类号 H01L21/027;H01L21/30 主分类号 H01L21/027
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