| 摘要 |
A gate signal generator comprises U- and X-phase set circuits (6U, 6X SIMILAR 8U, 8X) for discriminating, after the conduction period of every cycle, whether OFF time intervals (TN) of U- and X-phase thyristors (3U, 3X) are greater or smaller than a predetermined value, a reset circuit (9) for detecting that both the U- and X-phase circuits (6-8) do not provide outputs, a flip-flop (10) set in response to an output (FFS) from the U- or X-phase set circuit (6-8) and reset in response to an output (FFR) from the reset circuit (9), AND gates (70V, 70X) for calculating AND products of an output (FF) from the flip-flop (10) and U- and X-phase forward voltage signals (FVU, FVX) and for outputting the signals (F70U, F70X) at a start of the forward voltage application after setting the flip-flop (10), and OR gates (80U, 80X) for calculating OR sums of outputs (F70U, F70X) from the AND gates (70U, 70X) and outputs (GP5U, GP5X) from normal gate circuits (5U, 5X). Gate signals (GPU, GPX) are applied to the thyristors (3U, 3X) in response to the outputs (GPU, GPX) from the OR gates (80U, 80X). |
