A D-A converter in which the time constant of an integrating circuit (4) can be reduced and a high-speed operation becomes possible. The D-A converter is advantageous in that, if the amount of a ripple contained in an analog output of the converter is equal to that of the conventional converter, the time constant of the integrating circuit can be reduced with the result that the conversion speed can be improved. Separates most significant and least significant bits of digital input and treats separately. Most significant preset a down counter (2) whose output is combined with a divided clock signal (QL) by a gate circuit (15) to provide a signal (43). Least significant bits control a set of signals (Q3* to Q4*) derived from clock (Qo) in order to pseudo-randomise ripple-producing components and to provide second signal (41). Signals (41 and 43) are combined and integrated to produce analogue output.
