发明名称 MOUNTING STRUCTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To prevent the breakage due to thermal fatigue at a soldered connection part and to reduce a thermal stress exerted on a fine wiring part formed on an LSI chip by a method wherein a shear modulus of elasticity of a resin for a resin layer is made to be smaller than that of a low-melting alloy constituting a solder bump and its coefficient of thermal expansion is made to be nearly equal to that of the low-melting alloy. CONSTITUTION:After an LSI chip 2 where solder bump 3 are formed has been connected to and mounted on a substrate 5 by a flip-chip method, gaps around the solder bumps are filled with a resin 4 and are protected. During this process, the gaps are filled with the resin whose modulus of longitudinal elasticity is less than 1000kg f/mm<2> at the normal temperature, especially preferably in a range of 10-900kg f/mm<2>, and whose coefficiently of thermal expansion is in a range of 20-30X10-<6>/ deg.C at the normal temperature. Because the optimum resin of this kind is used, a multilayer wiring part of an aluminum thin film formed on a face of the LSI chip whose strength is weak is not broken down in an early stage; a characteristic of thermal fatigue is improved.
申请公布号 JPS63316447(A) 申请公布日期 1988.12.23
申请号 JP19870151190 申请日期 1987.06.19
申请人 HITACHI LTD 发明人 NAKANO FUMIO;AMAGI SHIGEO;SOGA TASAO;OTSUKA KANJI
分类号 H01L21/60 主分类号 H01L21/60
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