| 摘要 |
PURPOSE:To obtain a linear phase FIR type digital filter circuit for decimation capable of multiplying two data to be multiplied by the same coefficient after adding them, by providing a bidirectional shift register. CONSTITUTION:The shift register 11 provided with (n-1) stages outputs input data after delaying by (n-1) stages, and the shift register 12 provided with (n) stages outputs the input data after delaying by two stages, and a register 13 provided with one stage outputs an input after delaying by one stage. The bidirectional shift register 14 outputs plural inputted data in reverse sequence of inputting, and selectors 15a and 15b select and output one of two input data. In such a way, since the linear phase FIR type digital filter circuit for the decimation can multiply 17 the two data to be multiplied by the same coefficient after adding them in advance and the number of times of multiplication can be reduced to 1/2, it is possible to double the operating speed of a circuit.
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