发明名称 MEMORY INTEGRATED CIRCUIT
摘要 PURPOSE:To save remarkably the test expense by generating an address pattern, a write pattern and a collating pattern as test pattern to a memory section and incorporating a test means to test itself independently without using an external test machine. CONSTITUTION:A test circuit (TC) 21 uses an error control circuit (ECC) 12 in common to form an address pattern. On the other hand, as to data pattern, both write and collating patterns are formed by the TC21 independently. The TC21 applies the address pattern formed in this way to an MEM11 through a signal line st228, an operating mode designating terminal SW021, and an address information line sa15, and the write data pattern to the MEM11 through an st127, an SW122, and an sb16 respectively to write prescribed data information to the MEM11. The data information written in this way is read out through the sb16, the SW122, and the st127 so as to be compared with the collating data pattern formed independently. The write/collating are repeated for the number of times required for the test pattern used, and the final test result is outputted to a terminal R25, then the test is completed.
申请公布号 JPS5968900(A) 申请公布日期 1984.04.18
申请号 JP19820180385 申请日期 1982.10.13
申请人 NIPPON DENSHIN DENWA KOSHA 发明人 ISHIKAWA TSUTOMU
分类号 G11C29/00;G11C29/08;G11C29/12;G11C29/42 主分类号 G11C29/00
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