| 摘要 |
PURPOSE:To reduce the whole size of a chip and realize a high integrity by a method wherein a cell which has a transistor or a capacitor with a small ratio of a gate channel width to a gate channel length and is composed of a P<+> type diffused layer and an N<+> type diffused layer is added as a 2nd basic unit cell. CONSTITUTION:A 2nd basic unit cell 16 is inserted in a wiring channel 12 between 1st basic unit cell rows 11. The 2nd basic unit cell 16 is composed of polycrystalline silicon gates 17, a P<+> type diffused layer 18 and an N<+> type diffused layer 19 and one P-type channel transistor and one N-type channel transistor are formed in its foundation. In order to form a gate with a low speed operation, the ratio of the channel width to the channel length of the polycrystalline silicon gate 17 is smaller than that of the transistor of the 1st basic unit cell 12. With this constitution, when a delay circuit is necessary, it is not constituted by the 1st basic unit cells but an inverter is constituted by the 2nd basic unit cells and the delay time is prolonged by using it as a chain. |
