| 摘要 |
PURPOSE:To reduce a package size and improve the degree of freedom of the connection between chips by a method wherein 1st elements and a 2nd element are mounted three-dimensionally with via-holes provided in the 1st elements. CONSTITUTION:Via-holes 11 filled with conductor material respectively are provided in a plurality of 1st elements 10 composed of a semi-insulating substrate such as a GaAs substrate or an insulating substrate. Solder bumps 12 are provided at both the ends of each via-hole 11. Pads 14 for solder bumps are provided on one surface of a 2nd element 13 composed of an Si substrate, a semi-insulating substrate or an insulating substrate. The one bump 12 of the 1st element 10 is bonded to the pad 14 by controlled collapse bonding. The other bump 12 of the 1st element 10 is connected to the l/O pin 17 of a package 16 through a pattern 18. The 2nd element 13 and the 1st elements 10 are die- attached to a mounting stage.
|
