| 发明名称 |
INTERMEDIATE DECIMAL CORRECTION FOR SEQUENTIAL ADDITION |
| 摘要 |
<p>Appartus is provided to restore an excess six correct to every digit of an intermediate result which did overflow during the previous addition operation during a sequence of repeated BCD addition operations. A carry register is defined to store and feedback logical signals indicative the occurance of an overflow event.</p> |
| 申请公布号 |
CA1246746(A) |
申请公布日期 |
1988.12.13 |
| 申请号 |
CA19860512004 |
申请日期 |
1986.06.19 |
| 申请人 |
HEWLETT-PACKARD COMPANY |
发明人 |
MILLER, TERRENCE C. |
| 分类号 |
G06F7/494;G06F7/50;G06F7/508;(IPC1-7):G06F1/00 |
主分类号 |
G06F7/494 |
| 代理机构 |
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代理人 |
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| 主权项 |
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| 地址 |
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