| 摘要 |
PURPOSE:To reduce an exclusive area of a redundant circuit, and to improve the yield by forming a switching signal to a stand-by memory line or row by a programmable logic having a programming element. CONSTITUTION:In a programmable logic 5, at every unit address buffer AB0-ABi for constituting an address buffer circuit 1, each pair of fuses F01, F02-Fi1, Fi2 is provided in accordance with internal address signals a0, the inverse of a0-ai, and the inverse of ai being its output signals, one end of each pair of fuses is connected to an output terminal of the address buffer, and the other end is connected in common. This common connecting terminal is connected to one of input terminals of a multi-input NAND circuit 6, and one of each pair of fuses F01-Fi2 is connected by a laser, therefore, one of a true or false level is sent to the circuit 6. Accordingly, only when it has been decided that an address of each pair is a failure, in accordance with a failure address detected by a probe inspection, all inputs of the circuit 6 are set to a high level by cutting one fuse.
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