发明名称 CLOCK REGENERATION CIRCUIT
摘要 PURPOSE:To regenerate clock singles not only from demodulated data of a QPSK (Quardrature Phase-Shift Keying) system but also from that of an off set QPSK system with a simple circuit constitution by providing a modulation system decision circuit and a phase control circuit in additional to a clock regeneration circuit mainbody. CONSTITUTION:At the time of inputting demodulated data, the modulation system decision circuit B decides the demodulation system of demodulated data from the presence or absence of clock components outputted from the clock regeneration circuit mainbody, and the phase control circuit C supplies demodulated data to the clock regeneration circuit mainbody A as it is if the demodulation system of demodulated data has been decided to be the QPSK one in the modulation system decision circuit B. If the modulation system of demodulated data is decided to be the off set QPSK one, the circuit C supplies the I channel or the Q channel of demodulated data to the clock regeneration circuit mainbody A after it phase-shifts them by a 1/2 bit. Thus, the regeneration of the clock signals is attained as to demodulated data of the off set QPSK system in the same way as the case of demodulated data of the QPSK system.
申请公布号 JPS63290049(A) 申请公布日期 1988.11.28
申请号 JP19870124602 申请日期 1987.05.21
申请人 TOSHIBA CORP 发明人 ARAI MASANORI
分类号 H04L27/22 主分类号 H04L27/22
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