发明名称 CONTROL METHOD FOR PLL CIRCUIT
摘要 PURPOSE:To operate a PLL surely and stably by using a reference horizontal synchronizing signal, a reproduction horizontal synchronizing signal and a color burst signal as an input signal being an object of synchronization and using the three signals properly and switchingly to facilitate synchronizing locking. CONSTITUTION:A signal separation circuit 8 separates a horizontal synchronizing signal and a color burst signal included in a digital video signal and gives the result to a PLL circuit 9. The PLL circuit 9 generates a clock synchronously with the reproduced video signal and three signals, the reproduced horizontal synchronizing signal from the signal separation circuit 8, the color burst signal and the reference horizontal synchronizing signal from the reference signal generating circuit 10 are inputted as the object of synchronization. Then the three signals are used properly and switchingly in response to the state of the PLL. Thus, the synchronizing locking is facilitated and the PLL is operated stably and surely.
申请公布号 JPS63280590(A) 申请公布日期 1988.11.17
申请号 JP19870116614 申请日期 1987.05.12
申请人 PIONEER ELECTRONIC CORP 发明人 MORIYAMA YOSHIAKI
分类号 H04N5/12;H03L7/10;H03L7/199;H04N9/89;H04N9/896 主分类号 H04N5/12
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