| 摘要 |
If there is jitter in the input signal of a phase-locked loop, the low jitter frequencies, in particular, are inadequately suppressed and the clock frequencies generated are modulated with these jitter frequencies. The new method generates from an input clock frequency with jitter a jitter-free reference clock frequency from which the further clock frequencies can be generated without jitter. A phase-locked loop is used for generating a reference clock frequency. The control loop contains a narrow-band filter which, when a suitable oscillator frequency is selected, allows even low-frequency jitter frequencies to be blocked. A downstream divider prevents an instability in the control loop. The reference clock is to be used also in the master clocks for digital processing and transmission of broadband signals and in the signal generators of digital transmission links of the telecommunication networks for generating other clock signals. <IMAGE>
|
