| 摘要 |
PURPOSE:To perform the parity check with high efficiency without deteriorating the processing capacity by contg. a parity bit into a data input/output port of a dual port memory. CONSTITUTION:A dual port SRAM 1 contains two address input/output ports and two data input/output ports. Each address input/output port is connected to a CPU address bus 2 and a DMA address bus 5 respectively. At the same time, each data input/output port is connected to a CPU data bus 3 and a DMA data bus 6 respectively. In this case, each data input/output port consists of 9 bits and both buses 2 and 5 consist of 8 bits. A single bit of each data input/ output port serves as a parity bit lines 10 and 11 which are connected to the parity generating/checking circuits 4 and 7 respectively.
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