| 摘要 |
A delay circuit (10) includes a first inverter circuit (20) coupled between a first voltage source (VCC) and a reference potential by a plurality of parallel-connected transistors (Q5-Q19). Each of the transistors (Q5-Q19) has a control gate (DY1-DY15) which may be selected to bring the resistance of the transistor into circuit with the inverter circuit (20) to control the charging rate of a distributed capacitance. An output circuit (40) coupled to the first inverter circuit (20) provides the distributed capacitance and an inverted buffered output (DBUF). The output circuit also includes an output (DOUT) which may be connected to another circuit identical to the delay circuit (10) to form a cascaded delay circuit which can receive a reset signal for resetting the cascaded delay circuit. |
