INPUT/OUTPUT CIRCUIT

摘要

PURPOSE:To share plural processor modules which are put in asynchronous operation by enabling the outputs of 1st and 2nd data registers which hold data supplies from 1st and 2nd processor modules to be supplied selectively to a data input/output terminal. CONSTITUTION:Complementary switch control over MOSFETs Q5 and Q6 is performed and then central processing unit CPU and a timer counter TMCT holds necessary data in corresponding data registers DRGST1 and DRGST2 independently of each other. Data that the timer counter TMCT and central processing unit CPU output to the 1st data register DRGST1 and 2nd register DRGST2 can be fetched in them later and confirmed. Consequently, the timer counter TMCT and central processing unit CPU which are put in asynchronous operation can be shared.