MANUFACTURE OF SEMICONDUCTOR INTEGRATED CIRCUIT

摘要

A non-destructive double exposure method of examining photoresist features in section by, e.g., scanning electron microscopy, is described. The resist is exposed twice with one exposure defining integrated circuit features (5, 7, 9) and the other exposure defining an edge type feature (11) which overlaps an integrated circuit feature (5). Resist development produces a sectioned integrated circuit feature (17) which can be examined.