| 摘要 |
PURPOSE:To cover a difference in the setting up time at the time of manufacturing an IC with a simple constitution so as to utilize the IC effectively, by delaying clock pulses for writing in accordance with the set state of a flip flop (FF). CONSTITUTION:The distributing route of a clock signal distributing circuit 7 is designated by the output of an FF 8 and the output of the circuit 7 becomes the writing pulses of a write data latch 1 and write address latch 2. The output is also used as the writing pulse of a storage cell latch 4. If the FF 8 is set or reset by using a shift pass when a device is initialized, the value is held. When the setup time of 1-1 which is one bit of the latch 1 is longer than a standard, the FF 8 is reset and, when the setup time is shorter than the standard, the FF 8 is set. Clock signals are distributed through gates 20 and 21 at the time of setting the FF 8 and gates 22, 23, and 21 at the time of resetting the FF 8.
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