发明名称 GATE ARRAY SEMICONDUCTOR DEVICE
摘要 PURPOSE:To improve the degree of integration and the operation speed by arranging a first internal cell array having a small number of wiring channels and a second internal cell array having a large number of wiring channels as the internal cell arrays. CONSTITUTION:A title device includes a first internal cell array 4 which comprises a first wiring region 7 having at most two (namely, one or two) horizontal tracks and a first fundamental cell row R1, and a second internal cell array 5 which comprises a second wiring region 6 having at least 10 (e.g. 30) horizontal tracks and a second cell row R2 consisting of the same fundamental cells 3 as the first fundamental cell row R1. With this, the degree of integration improves and only a small area is required as the part wherein the wiring is placed on the internal cell arrays, so that the delay time due to the wiring capacity and the power consumption can be made small as compared with the spread-over type one.
申请公布号 JPS63249350(A) 申请公布日期 1988.10.17
申请号 JP19870083352 申请日期 1987.04.03
申请人 NEC CORP 发明人 YOSHIDA TAKETO
分类号 H01L21/82;H01L21/822;H01L27/04;H01L27/118 主分类号 H01L21/82
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