| 摘要 |
PURPOSE:To elucidate the cause of the stoppage of an external clock signal, by adding an external clock monitor circuit and generating a trigger signal or stopping the taking-in of data when no external clock is inputted within a set time. CONSTITUTION:A data signal 31 is inputted to an input circuit 11 and judged to be a high or low level to be sampled by an external clock signal 33. A trigger circuit 14 outputs a trigger signal when the sampled data coincides with the preset value. The sampled data is stored in a memory circuit 12 and displayed on a display circuit 13. The control clock signal 35 from a control circuit 15 and the signal 33 are applied to an external clock monitor circuit 17 which in turn outputs a forcible trigger signal 36 when the application of the signal 33 is stopped for a predetermined time. The signal 36 is applied to the circuit 15 through an OR gate 22 to generate a trigger signal 39. The signal 36 acts as data taking-in finish signal through an OR gate 23. Therefore, the stoppage cause of the signal 33 can be elucidated.
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