| 摘要 |
PURPOSE:To output optionally a control signal which has a control time corresponding to an output processing kind signal and to speed up operation by inputting initial values by processing kind signals generated by an initial value generation part to a timing signal generation part, and operating a timing signal generation part according to the initial values. CONSTITUTION:A L or H signal based upon the processing kind signal of the initial value generation part 7' is inputted as an initial value to a terminal D0 of the shift register SR 51 of a control signal generating circuit. Then when a refresh signal 2 is inputted, the output L of an OR gate 71 is loaded as an initial value onto the terminal D0 at the timing A of a clock 1 (CK) and the output H of an OR gate 72 is loaded as an initial value onto terminals D1-D3. In this state, an output 7 is sent out from terminals Q0-Q3 of the SR 51 and the output of the terminal D2 is inverted 52 and inputted to LOAD to reset an initial loading state. Every time the clock signal CK is inputted, shifting operation is repeated to hold the outputs of terminals D0-D3 at L, and when read signals 3 and 4 are inputted, the outputs of the terminals D0-D3 are held at H at specific timing.
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