| 摘要 |
<p>PURPOSE:To prevent the generation of double registration by a simple operation by inputting bit selecting signals corresponding to respective bit registers and a common data signal, and at the time of inputting a data signal when a prescribed bit selecting signal is effective, setting up its bit register and resetting other registers. CONSTITUTION:Address signals A1-A7 corresponding to respective bit registers R1-R7 and a common data signal Din are inputted to the registers R1-R7, only one signal out of the signals A1-A7 is made effective and other signals are invalidated. When the data signal Din is set up under a status that a certain address signal, e.g. A1, is effective, the register R1 corresponding to the signal A1 is set up, its output signal Dout 1 is turned to a high level e.g., other registers R2-R7 are reset, and their output signals Dout 2-Dout 7 are turned to low levels.</p> |
