| 摘要 |
PURPOSE:To obtain a phase locked circuit with simple constitution and fast response, by initializing a content held by a holding means on a frequency demultiplier means at the time of dissipating a holding command signal. CONSTITUTION:The holding command signal (e) is generated by setting a D-type flop-flop 10 by a reproduction reference signal (a). And a jump operation is started up, and when the reproduction reference signal (a) is outputted again after the lapse of a prescribed time since a monostable multivibrator 9 is triggered, the jump operation is completed, the D-type flip-flop 10 is reset, then, the holding command signal (e) is dissipated. Since the holding command signal (e) is supplied to an AND gate 6, the supplying of a clock to a frequency demultiplying counter 4 is stopped with the generation timing of the reproduction reference signal (a) just before the jump operation is started up, and a value just before the stoppage of the supplying of the clock is held at the frequency demultiplying counter 4. When the holding command signal (e) is dissipated, the supplying of the clock (c) to the frequency demultiplying counter 4 is restarted, and the counted value of the frequency demultiplying counter 4 is changed from a held value. In such a way, disturbance generated in a phase error signal (b) can be eliminated. |
